The Design of a Low Power Floating Gate Based Phase Frequency Detector and Charge Pump Implementation
نویسندگان
چکیده
منابع مشابه
A High Speed and Low Power Phase-Frequency Detector and Charge - pump
In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is over 1.2Ghz without additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the...
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In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less th...
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Nowadays, one of the most important blocks in telecommunication circuits is the frequency synthesizer and the frequency multipliers. Phase-frequency detectors are the inseparable parts of these circuits. In this paper, it has been attempted to design two new structures for phase-frequency detectors in QCA nanotechnology. The proposed structures have the capability of detecting the phase ...
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This paper presents a novel Phase frequency detector for Charge Pump Phase locked loop (PLL) applications to enable fast frequency acquisition in the phaselocked loop (PLL). To cope with the missing edge problem, the proposed PFD predicts the reset signal and blocks the corresponding input signal during the reset time. The blocked edge is regenerated after the reset signal is deactivated [1]. T...
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In this paper, the performance of two low power phase frequency detectors is compared. A modified D-FF based PFD reduces the power consumption of traditional PFD to 4.732uW at 40MHz clock frequency and dead zone to 40ps.It is suitable for low power applications. A Falling Edge PFD uses only 12 transistors. This PFD operates up to 1GHz at 1.8V supply voltage. It consumes only 5.5uW when operatin...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2013
ISSN: 0976-1527
DOI: 10.5121/vlsic.2013.4206